1. Field of the Invention
The present invention relates to semiconductor memories, and more particularly to a semiconductor memory which permits a remarkable increase in the capacitance of a storage capacitor portion without the necessity of increasing a plane area.
2. Description of the Prior Art
Regarding MOS dynamic memories, enhancements in the density of integration have been achieved at a proportion of about four times every three years since dynamic random access memories (hereinbelow, abbreviated to "dRAM") of 1 kb began to be sold early in the 1970's. However, 16-pin DIPs (dual in-line packages) have been chiefly used as packages for receiving memory chips, and besides, the sizes of cavities for receiving the chips have been limited. Therefore, the size of the memory chip has increased to only, at most, 1.4 times in spite of the quadrupled magnitude integration. Accordingly, the area of a memory cell corresponding to one bit which is the unit memory capacity has decreased remarkably with the enhancement of the density of integration and has become as small as about 1/3 with the quadrupled magnitude of integration. The capacitance C of a capacitor is denoted by C=.epsilon.A/t (where .epsilon.: the dielectric constant of an insulating film, A: the area of the capacitor, and t.. the thickness of the insulating film), so that when the area A becomes 1/3, also the capacitance C becomes 1/3 as long as the quantities .epsilon. and t are held constant. The magnitude of a signal, S as the storage capacitor is proportional to the quantity of charges, Q, which in turn is the product between the capacitance C and a voltage V. Therefore, when A becomes small, Q decreases proportionally, and S decreases accordingly.
Letting N denote noise, the S/N (signal-to-noise) ratio becomes small with decrease in S, and this poses a serious problem in circuit operations. It has accordingly been common practice to compensate the decrement of A by the decrement of t. As the scale has enlarged (the density of integration has risen) to 4 kb, 16 kb and 64 kb, the thickness of a typical SiO.sub.2 film has gradually decreased to 100 nm, 75 nm and 50 nm by way of example.
Further, it has recently been confirmed that charges of about 200 fC are generated within a Si substrate by .alpha.-particles which are emitted from radioactive heavy metals (U, Th etc.) contained in the package etc., and that they form noise. From the standpoint of a high reliability operation, it has become difficult to render the signal magnitude Q below approximately 200 fC.
Accordingly, it has become practice to make the insulating film still thinner. It has then turned out that the dielectric breakdown of the insulating film is problematic. The dielectric breakdown field of SiO.sub.2 is 10.sup.7 V/cm at the maximum. Accordingly, an SiO.sub.2 film 10 nm thick is nearly permanently broken down or is deteriorated by applying 10 V thereto. When the reliability over a long term is taken into account, the smallest possible voltage below the maximum breakdown voltage needs to be used. It is therefore difficult to make the insulating film of the capacitor very thin.
That is, in order to enhance the density of integration of a semiconductor memory without incurring such problems as the lowering of the S/N ratio, the disturbance ascribable to the .alpha.-particles and the dielectric breakdown, the required area of a memory cell must be reduced by keeping or increasing the electrode area of a capacitor without thinning the insulating film of the capacitor.
In this regard, however, the storage capacitor portion of the conventional dynamic memory has been formed of a semiconductor substrate, and an insulating film and a plate (conductor film) which are stacked and deposited on the surface of the semiconductor substrate. In order to simultaneously reduce the required area of the memory cell, accordingly, there is no other way than decreasing the electrode area of the capacitor. This has formed a serious hindrance to the enhancement of the density of integration of the semiconductor memory.
To the end of solving such problems, it has been proposed to form a recess in a semiconductor substrate and to utilize the recess for a capacitor (Japanese Patent Application Publication No. 56-48976, Japanese Patent Application Laying-open No. 51-130178, which corresponds to U.S. Pat. No. 3,962,713). The proposal, however, does not refer to the decrease of the area of an isolation region among semiconductor elements. The required area of a semiconductor memory must be further reduced in order to fabricate an integrated circuit having an extraordinarily high density of integration.